1. Field of the Invention
This invention relates to electronic device fabrication and, more particularly, device fabrication involving doped layers.
2. Art Background
In most electronic components, such as integrated circuits, lateral separation is produced between regions of essentially single crystal silicon, i.e., silicon having less than a total of 10.sup.10 cm.sup.-2 defects, e.g., linear and planar defects such as dislocations or stacking faults, respectively. This separation is accomplished by interposing between the single crystal silicon regions, a region of electrically insulating material having a thickness approximately equal to the depth of the active regions of the single crystal materials being separated. (The active region is that portion of the single crystal silicon which is modified to contain electronic device structures. The active region is typically 1 .mu.m thick for nominal voltage devices.) Alternatively, a p-n barrier separates the device regions. In this manner, transistors or other devices formed in one single crystal region, i.e., one active region, are electrically isolated and are prevented from interacting with devices in a second active region.
Vertical isolation, in addition to lateral isolation, is advantageously employed in devices operating at nominal voltages where enhanced reliability is desired or in devices designed for high voltage operation. This vertical isolation is provided by underlying some, or most commonly all, of the single crystal silicon regions with a region of electrically insulating material. The additional insulating material providing vertical isolation prevents electron hole pairs formed in the underlying substrate by thermal processes or by ionizing radiation from migrating to an active region. Thus, errors in the processing of information by this migration are avoided. The vertical isolation also reduces capacitance and thus allows faster device operation. Additionally, for high voltage operation the vertical isolation prevents conduction induced by high voltage between active regions through the silicon substrate.
Various processes have been employed to produce a component having both lateral and vertical isolation. In one process described by Celler, et al, Journal of the Electrochemical Society, 132, 211 (1985), a silicon dioxide lined tube is produced in a silicon wafer. This tub is filled with polycrystalline silicon that is transformed into a single crystal region through appropriate high temperature thermal processing. In a second process oxygen is implanted into the silicon wafer and a silicon oxide buried region is subsequently formed by a high temperature annealing procedure. Thus, in general, the production of dielectrically isolated devices requires a high temperature treatment. (See also P. L. F. Hemment, Materials Research Society Symposium Proceedings, Vol. 33, pages 41-51 (1984).)
For certain applications such as electronic switching, e.g., switching in telecommunication systems, it is desirable to produce devices utilizing a buried conductive layer adjacent to the silicon dioxide isolating layer. For example, as shown in FIG. 1, a dielectric isolating region, 5, is utilized in conjunction with a drain and source (13 and 14 respectively) and a gate, 15. The buried conductive region, 16, acts as a drain. Similarly, in a bipolar configuration, an emitter, 20, a base, 21, and a dielectric region, 30, are employed. A buried conductive layer, 31, is utilized as the collector. In either configuration, a vertical orientation is utilized to decrease the resistance of the device in the on state and thus to increase the current flow. Additionally, this vertical device structure utilizes less single crystal silicon material and as a result allows a higher density of transistors within a dielectrically isolated region.
For fabrication schemes employing a high temperature treatment, e.g., a recrystallization process or a chemical segregation process, forming the conductive buried layer and maintaining the conductivity within a relatively limited spatial region is difficult. Typically, the high conductivity is produced by introducing a dopant into the region where enhanced electrical conductivity is required. Since this region is adjacent to a dielectric layer, it is often formed before the overlying silicon is deposited. Thus, any thermal treatment of the silicon in turn subjects the deposited region to an equivalent heat treatment. The effect of relatively high temperatures on the doped region is to cause an isotropic diffusion inducing concomitantly undesirable spatial broadening of the doped region. This effect is particularly pronounced when the thermal process involves melting. Clearly, any dopant present or diffused into the melted region is rapidly distributed. Thus, although certain advantageous techniques for producing dielectrically isolated devices have been developed, the flexibility of techniques depending on high temperature treatment, e.g., greater than 1250.degree. C., has been somewhat limited to producing structures which do not require a buried conductive region.